A computer processes more content, and if only a dominant frequency of a single-core processor is increased, excessive heat is generated and performance cannot be correspondingly improved; therefore, a multi-core processor appears. A multi-core technology enables a computer to process tasks in parallel, exchanging time for space, and greatly improving performance of the computer. A design architecture of the multi-core processor is mainly classified as a synchronous (symmetric) architecture or an asynchronous (asymmetric) architecture. Processors in the synchronous architecture share all system resources, and processors in the asynchronous architecture manage respective resources.
In a symmetric multiprocessing (Symmetric Multiprocessing, SMP) architecture shown in FIG. 1, system resources are shared by all processors in a multi-core processor, a synchronous level 2 cache is used, all the processors use a same frequency and supply voltage, a system cannot adjust the frequency and the supply voltage for each core according to a usage rate, the level 2 cache is shared by all the processors, and a frequency of the level 2 cache cannot be individually adjusted for each processor.
When usage rates of all cores in the system are unbalanced, because in the SMP architecture, all the processors use a same frequency and supply voltage, a frequency and a supply voltage of a processor with a smaller task usage rate need to be subject to a frequency and a supply voltage of a processor with a larger task usage rate, which makes the frequency and the supply voltage of the processor with a smaller task usage have relatively large values, causing energy waste.
In an asymmetric multiprocessing (Asymmetric Multiprocessing, ASMP) architecture shown in FIG. 2, an asynchronous level 2 cache interface is used, and frequencies and supply voltages of all processors and level 2 caches can be separately adjusted according to a system usage rate.
When a hit rate of a level 1 cache of a processor is relatively low, data needs to be acquired from a level 2 cache. Because in the ASMP architecture, speeds of level 2 caches corresponding to processors can be separately adjusted according to a processor usage rate, if data to be acquired in this case is in a level 2 cache corresponding to a processor with a lower frequency, the processor needs to wait for a longer time before obtaining the data from a level 2 cache with a lower frequency; or if data to be acquired in this case is in a level 1 cache corresponding to a processor with a lower frequency, the processor needs to wait for a longer time before obtaining the data from the level 1 cache for the processor with a lower frequency. A longer processor waiting time decreases an actual usage rate of a processor, and within the waiting time, the processor is in a high-frequency and high-voltage state, affecting system power consumption.